Vogls: A Verilog Simulator

Hello nice people of Reddit,

For the past 7 months, as part of my PhD, I have been working on a Verilog simulator, and since the paper just got accepted, I can finally share it.

Verilog is the language used to describe hardware designs, especially heavily as you get closer to the final gate-level netlists. Vogls takes these designs and simulates them according to the Verilog 2005 scheduling semantics.

Repository: https://codeberg.org/coastalwhite/vogls
Preprint: https://arxiv.org/abs/2607.15782

We use this simulator to do pre-silicon side-channel analysis, which typically involves capturing a bunch of signal traces around a short point-of-interest. There was no simulator that allowed full-timing simulation and was versatile enough to do what we wanted, so we built our own. It is currently still very much alpha software, but we use it to do research, and it can simulate many designs such as masked AES cores, RISC-V processors, and floating-point accelerators.

A few things that it has:

• A bytecode and compiled backend
• A Python library that you declaratively describe side-channel analysis plans in
• Standard Delay Format (SDF) and specify block support.

To prove to myself it can be used as a library in tools, I also created Pipeline Explorer which uses Vogls under the hood to simulate and inspect the pipeline cycle-by-cycle for several RISC-V CPUs.

There is still much to do, but I am thrilled to share this now.

AI disclosure (because people will ask): I did not use any AI for the main codebase except for the equivalent of googling. I did use AI for three main things:

1. Debug large Verilog designs that did something wrong and reduce to MREs.
2. Prototype Pipeline Explorer, but after the performance of the UI was horrible, I rewrote most of it by hand in vanilla JS and canvas.
3. The temporary testing infrastructure for the small RISC-V assembler I wrote is also AI. I will likely remove this at some point because it is unreadable.